Some new details have emerged regarding Intel’s 12th generation of Alder Lake-S Core processor lineup. As you may already know by now that Alder Lake-S Core processors are said to be the company’s first 10nm SuperFin-based mainstream desktop SKUs. We have also seen documents, datasheets, and release notes for these CPUs which have also appeared on Intel’s own developer website.

These CPUs have been rumored to leverage the high-velocity PCIe 5.0 interface. Alder Lake CPU lineup will bring the concept of heterogeneous multi-core to x86 processors for consumer and client PCs. High-end Alder Lake CPUs are expected to have up to 16 cores.

Alder Lake-S CPU lineup will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. Alder Lake will also be the first to bring DDR5-4400 RAM, AV1 accelerated encode, GNA 3.0, Wi-Fi 6E, and PCIe Gen5 support along with new security extensions. For more technical details please kindly refer to this most recent article.

Early rumors have pointed out that Alder Lake processors could support both the PCIe 5.0 and PCIe 4.0 standard, and now a recent code snippet seems to confirm that. Some information has been spotted in Coreboot, by Komachi_Ensaka. In case you didn’t know, Coreboot is basically an open-source alternative for UEFI.

Formerly known as LinuxBIOS, Coreboot is a software project aimed at replacing proprietary firmware (BIOS or UEFI) found in most computers with a lightweight firmware designed to perform only the minimum number of tasks necessary to load and run a modern 32-bit or 64-bit operating system. Some valuable information on the potential PCIe configuration pertaining to the Alder Lake CPU lineup has been spotted.

However, the code specifically references the Alder Lake-P (ADL-P) SKU, instead of the Alder Lake-S lineup. So it is slightly unclear whether the same PCIe 5.0 support configuration will also translate to the Alder Lake-P desktop CPU lineup, but the chances are most probably high. We are still not fully sure what Alder Lake-P codename targets, but according to previous speculation we can think it could be similar to Intel’s Atom P-series, a mobile chip, and/or a server variant.

Intel’s Alder Lake 12th-gen processors will come in three different flavors; Alder Lake-S for desktop, the Alder Lake-P configuration used on Atom Server series, just like the previous “P series” from Intel, and lastly the “M series” targeting mobile devices.

In any case, a previous coreboot patch has revealed that Alder Lake-P CPU lineup could max out at 14 cores, thus sporting six Golden Cove Big cores, and eight Gracemont Small cores.

From the most recent coreboot code entry we can see that the Alder Lake-P CPU appears to provide a very flexible PCIe layout. The processor reportedly offers one PCIe 5.0 x8 lane, or two PCIe 4.0 x4 lanes.

However, it appears that neither PCIe interface supports bifurcation, which means we cannot split up the PCIe 5.0 gen lane, or get the PCIe 4.0 lanes to operate at x8 speeds. Nonetheless, both the PCI-e Gen 5.0 and 4.0 interfaces are backwards compatible with previous-gen devices.  

PCIe bifurcation actually refers to splitting 1 PCIe Port into 2 or more with smaller lane width. This is a function of the CPU in most cases. Most recent CPUs support this. Single most important factor is BIOS/UEFI support.

By default lots of mainstream ATX Mainboards actually use PCIe bifurcation to either provide one x16 Slot or two x8 Slots for SLI/Crossfire via simple signal switches. Downside of this setup is that even if one device is idle, the other one is limited to x8 speed. The more expensive Mainboards may use often so called “PEX” or “PLX” Chips, which are actually PCIe packet switches that can distribute the upstream x16 Port into two or more downstream Ports, thus enabling a single card to get all x16 bandwidth, if the other ones are idle.

PCIe Bifurcation does not decrease the speed but only splits/bifurcate the lanes. In order to use bifurcation, the motherboard should support it and the BIOS should support it as well.

Coming back to the Alder Lake CPU PCIe support, a single PCIe 5.0 x8 lane might still provide plenty of bandwidth. PCIe 5.0 x8 is essentially equivalent to PCIe 4.0 x16, so the interface is good for up to 32 GBps of bandwidth.

AMD’s current Ryzen 3000 and Ryzen 5000 series of processors support the PCIe 4.0 standard, and Intel’s upcoming Rocket Lake-S desktop CPU lineup will also get the same PCIe 4.0 treatment.

As per one old coreboot leaked code, spotted by @davideneco25320 back in August 2020, the full configuration of the Alder Lake series of CPUs, namely the CPU, GPU and the PCH was detailed to some extent. It appears we would be getting several Alder Lake CPU variants, in the Alder Lake S and P-Series configurations. This can get a bit confusing though because of the “segmentation”.

For example, the reported config numbers ‘8+8+1’ actually refer to the BIG, SMALL, and GPU core counts respectively. So we assume all variants will indeed have the Small cores on desktop as well. So expect a maximum of 2 to 8 big cores, and up to 0 to 8 small cores.

Some internal codenames for the Platform Controller Hub (PCH) were also leaked before. It seems that Intel will use four PCHs with distinct features to cater to different market segments. These appear to be the Base, Mainstream, Premium and the Super Tier platforms.

• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, “Alderlake-P-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, “Alderlake-P-Super SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, “Alderlake-P Premium SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, “Alderlake-P Mainstream SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, “Alderlake-P-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, “Alderlake-P-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, “Alderlake-P Super SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, “Alderlake-P Premium SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, “Alderlake-P-Base SKU” },
• […]
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, “Alderlake-S-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, “Alderlake-S-Super SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, “Alderlake-S Premium SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, “Alderlake-S Mainstream SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, “Alderlake-S-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, “Alderlake-S-Base SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, “Alderlake-S Super SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, “Alderlake-S Premium SKU” },
• { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, “Alderlake-S-Base SKU” }

It remains to be seen what kind of PCIe configuration the Alder Lake-S platform will support when Intel finalizes these 10nm chips for the desktop market. These processors will debut as the 12th generation core lineup next year, the second half of 2021 that is.

Stay tuned for more tech news!