Intel’s 12th next generation of Alder Lake-S Core processors are said to be the company’s first 10nm mainstream desktop processors, and we have already seen documents, datasheets, and release notes for these CPUs which also appeared on Intel’s own developer website. These processors have been confirmed to support a new LGA1700 socket. This socket will have support for at least three generations of Intel CPUs.

Now, according to a recent finding as reported by Phoronix, some new GNU compiler GCC 11 updates have been released, which further hints that Intel will release a new hybrid CPU architecture, which combines big cores with smaller cores, for desktop PCs when the Alder Lake-S CPUs arrive. Intel’s Alder Lake-S CPUs are going to succeed the Rocket Lake-S lineup, which will land early next year.

According to previous leaks, these new chips have been confirmed to support a new Hybrid Architecture, aka ‘big core/small core’ design, featuring Golden Cove and Gracemont cores. Alder Lake-S will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors.

The new GNU compiler update as posted by Phoronix includes a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips, with Alder Lake noticeably missing support for AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips. These instructions are also disabled in Intel’s hybrid Lakefield chips. This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores.

Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid architecture design to desktop PCs.

However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores. So this also means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner.

The Sapphire Rapids chips on the other hand support many AVX instructions, like for example AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, and the new AVX512BF16 that enables support for bfloat 16, which is a compact numerical format having similar performance to FP32, but with only half the bits.

The Alder Lake-S CPU architecture will also feature the CLDEMOTE ‘cache line demote instruction’ set, which I’ve explained in details in my previous article. Though, to reiterate, the CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved (demoted) from the cache(s) closest to the processor core to a level more distant from the processor core.

CLDEMOTE instructions are used so that the OS can tell the processor core which specific line in the cache is no longer needed, and its contents can be moved elsewhere, however, not directly into the main operating memory, but still into the processor cache, at higher levels (from L1 to L2 and from L2 to L3).

These upcoming Alder Lake CPUs would be featuring up to 16 cores, in which 8 would be Big, and the rest would use the Small architecture, assuming all the past rumors and recent findings are accurate.

The LGA 1700 socket is getting a support for 3 generations of Intel CPUs. This is something new for INTEL because the company has been known to support a short socket lifespan till now. These rumors also indicate that Intel’s LGA1700 socket will compete with AMD’s AM5 socket in terms of platform longevity.