Intel recently gave an update to analysts and investors on two crucial CPU projects of the company, namely the client desktop PC Alder Lake CPU lineup, and Sapphire Rapids chips for the HPC/server market.

Intel provided us with some additional details, apparently stating that Alder Lake is currently sampling to customers, whereas Sapphire Rapids is about to sample in the fourth quarter. Intel will launch servers based on Sapphire Rapids sometime in early or late 2021.

During the company’s earnings call with analysts and investors Bob Swan, CEO of Intel said, “We are now sampling our 2021 client CPU Alder Lake, and we’ll be sampling our 2021 data center CPU, Sapphire Rapids later in the fourth quarter. Both will deliver significant capabilities enabled by our six pillars of innovation including our [10nm] Enhanced SuperFin technology.”

Intel’s 12’th generation of Alder Lake-S Core processors are said to be the company’s first 10nm SuperFin-based mainstream desktop processors, and we have already seen documents, datasheets, and release notes for these CPUs which also appeared on Intel’s own developer website.

The 10 nm Enhanced SuperFin process technology was originally designed for datacenter/HPC market segment and its products in mind, to provide enhancements to the power delivery system, MEOL and BEOL etc, in semiconductor terms.

Alder Lake processors have been confirmed before to support a new LGA 1700 socket as well, as shown below.

As the name implies, the LGA1700 socket is comprised of 1,700 pins, which gives us 500 more pins that the existing LGA1200 socket that houses Comet Lake-S and the upcoming Rocket Lake-S series of processors. The upcoming LGA1700 socket board will have support for three generations of CPUs.

We can see that the socket dimensions for LGA1700 are 37.5mm x 45mm, which is about 7.5mm taller than Intel’s current LGA1200 socket. The bigger size is to house larger core counts than the Rocket Lake-S lineup which are currently planned for release in the first quarter of 2021, as confirmed by Intel on its official blog.

From the picture we can see the Alder Lake CPU having a more rectangular shape, a new larger form factor, whereas the LGA1200 socket is square shaped. So Alder lake processors won’t be compatible with existing Motherboard chipsets, as they will require a new socket LGA1700 Motherboard.

The land grid array pin layout remains the same as evident from the die picture, and there are a total of 1700 gold contact pads as well.

Alder Lake CPU lineup brings the concept of heterogeneous multi-core to x86 processors for client PCs. High-end Alder Lake CPUs are expected to have up to 16 cores. And we’ve already seen one Alder Lake-S CPU sample sporting 16 physical cores and 32 threads before.

Back in July, Intel confirmed that its next-gen 10nm Alder Lake-S CPU lineup will launch in the second half of 2021. Intel has also confirmed that the next-gen Alder Lake-S CPUs will use a new Hybrid Core/Atom processor architecture. These next-gen CPUs are expected to support the DDR5 memory and PCIe 5.0 interface.

Back in August Intel emphasized on the performance aspect of Alder Lake CPUs. “We are advancing our hybrid architecture significantly with the focus on performance,” said Raja Koduri, chief architect at Intel. “We are working on next generation hardware, guided scheduler, optimize for performance and leveraging all close seamlessly. Alder Lake will not only be great for performance, but it will also be our best performance per Watt architecture.”

Alder Lake-S CPU lineup will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. Alder Lake-S would feature an 8+8 core configuration, in which half the cores are going to be Big Cores and the rest of the remaining would be Small Cores. These processors would thus feature a total of 16 cores in a single package, initially.

According to one report these architectures are Golden Cove (Willow Cove successor) and Gracemont (Tremont successor), respectively. Willow Cove is expected to appear in the upcoming Rocket Lake-S series of processors.

On the server side, Intel is supposed to focus and start volume production of its Sapphire Rapids processors because the company has at least one supercomputer contract, dubbed as Crossroads that needs to be delivered on time. NNSA’s Crossroads supercomputer will use HPE’s Cray EX clustered architecture that use blades and liquid cooling.

Crossroads will replace the existing Trinity supercomputer and will be used by scientists at Lawrence Livermore, Los Alamos, and Sandia National Laboratories to support the Stockpile Stewardship Program, current and planned weapons Life Extension Program activities, and future predictive weapons research and calculations.

It will also feature Intel’s future Xeon Sapphire Rapids processors with an advanced memory architecture that will enable much faster data movement. Crossroads will have four times greater overarching system performance and enable easier code portability than its predecessor Trinity system.

Just to recap some of the previous findings/leaks on Alder Lake Platform specs.

Back in July, a new GNU compiler update was posted by Phoronix, which included a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips, with Alder Lake noticeably missing full support for the AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips.

These instruction sets are also disabled in Intel’s latest hybrid Lakefield chips. This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores.

Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid core architecture design to desktop PCs.

However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores. So this means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner.

The Sapphire Rapids chips on the other hand support many AVX instructions, like for example AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, and the new AVX512BF16 that enables support for bfloat 16, which is a compact numerical format having similar performance to FP32, but with only half the bits.

The Alder Lake-S CPU architecture will also feature the CLDEMOTE ‘cache line demote instruction’ set, which I’ve explained in my previous article. Though, to reiterate, the CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved (demoted) from the cache(s) closest to the processor core to a level more distant from the processor core.

CLDEMOTE instructions are used so that the OS can tell the processor core which specific line in the cache is no longer needed, and its contents can be moved elsewhere, however, not directly into the main operating memory, but still into the processor cache, at higher levels (from L1 to L2 and from L2 to L3).

Also, according to one recent report posted by Zhihu, the new hybrid Technology in the upcoming Alder Lake architecture would allow both CPU cores (small and big) to share the same instruction set and registers, but the actual availability of certain instructions would depend on which core is actually enabled and active.

The user also shared a screenshot from Intel’s internal document which suggests that the following AVX-512, TSX-NI, and the FP16 instruction sets will be disabled when the Hybrid Technology is enabled (both Big and Small cores are enabled at the same time).

The instructions will only work when the hybrid technology is disabled, which means the Small cores are disabled. By disabled we can think of the processor’s mode/PL state, though I need more technical info to confirm how this will work on Desktop PCs.

Both the big and small cores will have the same amount of instruction sets and model-specific registers, but will have different computational powers, and the overhead will also differ.

We can assume the big cores to have higher throughput and clock speeds, whereas the small cores are going to be more power efficient. Like mentioned before, the following instruction sets, e.g. AVX512, Intel TSX and FP16, are only going to work on the Big cores. ARM’s Big/Small core architecture makes more sense for mobile devices, to conserve power, but we still don’t know how this Hybrid technology is going to actually work on Desktops.

Intel has not announced any exact launch date for Alder Lake-S processors yet, but since the Alder Lake-S is the successor to Tiger Lake, so the processors will debut as the 12th Generation Core lineup next year, second half of 2021.

Stay tuned for more!