In a recent 2020’s second-quarter earnings press release, Intel confirmed that the next-gen Alder Lake-S CPU lineup will launch in the second half of 2021. Intel has also confirmed that their 7nm products have been delayed for at least 1 year.

Intel’s next generation of Alder Lake-S Core processors are said to be the company’s first 10nm-based mainstream desktop processors, and we have already seen documents, datasheets, and release notes for these CPUs which also appeared on Intel’s own developer website. These processors have been fully confirmed to support a new LGA1700 socket. These next-gen CPUs are also expected to support the new DDR5 memory and PCIe gen 4.0 standard/interface.

As the name implies, the LGA1700 socket is comprised of 1,700 pins (42% more pins), which gives us 500 more pins that the existing LGA1200 socket that houses Comet Lake-S and the upcoming Rocket Lake-S series of processors. The new LGA1700 socket will have support for at least three generations of Intel CPUs. This is something new for Intel because the company has been known to support a short socket lifespan till now. Intel’s LGA1700 socket will compete with AMD’s AM5 socket in terms of platform longevity.

Alder Lake-S CPU lineup will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. Alder Lake-S would feature an 8+8 core configuration, in which half the cores are going to be Big Cores and the rest of the remaining would be Small Cores. These processors would thus feature a total of 16 cores in a single package. According to one report these architectures are Golden Cove (Willow Cove successor) and Gracement (Tremont successor), respectively. Willow Cove is expected to appear in the upcoming Rocket Lake-S series of processors. Few months back, it was reported that Alder Lake-S processor will be available in three combinations. For example, the reported configuration numbers 8+8+1 actually refer to the BIG, SMALL, and GPU core counts respectively.

Now a recent SiSoftware database submission as spotted by @_rogame sheds some light on what to expect from the upcoming Alder Lake hybrid chip’s iGPU. The recently discovered SiSoftware entries show the Alder Lake-S iGPU having 32 Execution Units (EUs), which amounts to a total of 256 shader cores. The clock speed of these shader cores maxes out at 1.15 GHz. The entry-level chips are typically the ones that will sport 32 EUs. This setup entry might be just one of the many different combinations we have seen before for Alder Lake, in which the series were shown to feature 2 to 8 big cores, and 0 to 8 small cores, respectively.

Existing Ice Lake processors come with the Gen11 Xe graphics. For example if we take the Core i3-1000G1 and Core i5-1035G1 CPUs, both of these chips come with 32 EUs. The iGPU for the i3-1000G1 is clocked at 900 MHz, while the i5-1035G1 has 1.05 GHz speed as peek. This new Alder Lake-S engineering sample appears to have a slight performance uplift of 100 MHz give or take. This could also mean slightly better performance than the current Ice lake lineup. Other Alder Lake-S core configurations may have a clock speed higher than 1.15 Ghz. Since the iGPU of Alder Lake-S seemingly also has more cores than the current ‘Comet Lake-S’ CPU lineup, we can expect better performance out of these chips.

Back in July, a new GNU compiler update was posted by Phoronix, which included a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips, with Alder Lake noticeably missing support for AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips. These instruction sets are also disabled in Intel’s latest hybrid Lakefield chips. This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores.

Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid core architecture design to desktop PCs.

However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores. So this means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner. The Sapphire Rapids chips on the other hand support many AVX instructions, like for example AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, and the new AVX512BF16 that enables support for bfloat 16, which is a compact numerical format having similar performance to FP32, but with only half the bits.

The Alder Lake-S CPU architecture will also feature the CLDEMOTE ‘cache line demote instruction’ set, which I’ve explained in details in my previous article. Though, to reiterate, the CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved (demoted) from the cache(s) closest to the processor core to a level more distant from the processor core. CLDEMOTE instructions are used so that the OS can tell the processor core which specific line in the cache is no longer needed, and its contents can be moved elsewhere, however, not directly into the main operating memory, but still into the processor cache, at higher levels (from L1 to L2 and from L2 to L3).

Also, according to one recent report posted by Zhihu, the new hybrid Technology in the upcoming Alder Lake architecture would allow both CPU cores (small and big) to share the same instruction set and registers, but the availability of certain instructions would depend on which core is actually enabled and active. The user also shared a screenshot from Intel’s internal document which suggests that the following AVX-512, TSX-NI, and FP16 instructions will be disabled when the Hybrid Technology is enabled (both Big and Small cores are enabled at the same time).

The instructions will only work when the hybrid technology is disabled, which means the Small cores are disabled. By disabled we can think of the processor’s mode/PL state, though I need more technical info to confirm how this will work on Desktop PCs. Both the big and small cores will have the same amount of instruction sets and model-specific registers, but will have different computational powers, and the overhead will also differ. We can assume the big cores to have higher throughput and clock speeds, whereas the small cores are going to be more power efficient. Like mentioned above, the following instruction sets AVX512, Intel TSX and FP16, are only going to work on the Big cores. The ARM’s Big/Small core architecture makes more sense for mobile devices, to conserve power, but we still don’t know how this Hybrid technology is going to actually work on Desktops.

Intel has not announced any exact launch date for Alder Lake-S processors yet, but since the Alder Lake-S is the successor to Tiger Lake, so the processors will debut as the 12th Generation Core lineup next year, second half of 2021.