Just few days ago I explained in one article about the lack of AVX-512 instruction support on Intel’s next-gen Alder Lake-S CPUs. Now, Linux and Git creator Linus Torvalds has commented on this, and shared his own views on the AVX-512 instruction set (Advanced Vector Extensions 512) found on select Intel processors.

In a mailing list discussion stemming from a Phoronix article this week on the compiler instructions Intel is enabling for Alder Lake (and Sapphire Rapids), Linus Torvalds chimed in. The Alder Lake instructions being flipped on in GCC right now made no mention of AVX-512 but only AVX2 and others, likely due to Intel pursuing the subset supported by both the small and large cores in this new hybrid design.

Torvalds’ strong advice to Intel was to focus on things that matter the most, instead of wasting resources and time on new instruction sets, like e.g. the AVX-512, that aren’t beneficial outside of the HPC market.  Though, his point of view does make sense in this context. He also had this to say, “I hope AVX512 dies a painful death”.

Torvalds also cautioned against placing too much weightage on floating-point performance benchmarks, particularly those that take advantage of exotic new instruction sets that have a fragmented and varied implementation across product lines.

Intel’s Xeon Phi x200 processor (codenamed as “Knights Landing”) which debuted in 2016 had support for the AVX-512 instruction set. However, the instruction set later was implemented in Intel’s other processor lineups such as the Skylake-SP, Skylake-X, Cannon Lake and Cascade Lake. Intel’s both Cooper Lake and Ice Lake processors also support select AVX-512 instruction subsets. While ‘Alder Lake’ processors seemingly lack AVX-512 support, Tiger Lake will exploit this instruction set, as confirmed by the chipmaker.

Now, many feel that just because AVX-512 support is useless to ‘Linus Torvalds’ doesn’t mean other people and organizations can’t find a use for them. Here is my take on this whole issue: ‘Intel AVX-512 can indeed accelerate performance for workloads and use cases such as scientific simulations, financial analytics, artificial intelligence (AI)/deep learning, 3D modeling and analysis, image and audio/video processing, cryptography, and even data compression’.

But for the average home user/gamer AVX-512 is irrelevant. Intel’s AVX-512 can also help data centers more efficiently use available storage resources. Simply put, it accelerates storage functions, such as (de)duplication, encryption, compression, and decompression. It accomplishes this by doubling the number of bits in the register from 256 to 512. In fact, it calculates storage functions in half the time of the previous generation. This acceleration has a number of use cases:

• 63 times faster high-performance computing*
• 2 times faster AI/deep learning*
• 1 times faster cryptographic hashing performance*
• 2 times faster data protection*

This exceptional processing of encryption algorithms helps reduce the performance overhead for cryptography, which means you can deploy more secure data and services into distributed environments without compromising performance. So this means for the Enterprise/HPC segment, this instruction may prove more beneficial, and not for the basic home user. But nonetheless, if Intel is dropping support on Alder Lake-S lineup of CPUs, then there might be some reason behind it, apart from the Hybrid architecture which the company plans to implement.

Linus Torvalds’ full opinion and mail on AVX-512 can be viewed here. In case you didn’t know Linus Torvalds recently upgraded to an AMD Ryzen Threadripper 3970X processor powered machine after 15 years of using Intel processors for his work.

To reiterate, the previous new GNU compiler update as posted by Phoronix includes a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips, with Alder Lake noticeably missing support for AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips. These instructions are also disabled in Intel’s hybrid Lakefield chips.

This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores. Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid architecture design to desktop PCs. However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores.

So this also means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner.